EOS RPO

Senior Staff Design Verification Engineer

Posted Apr 21, 2026
Project ID: 20025895
Location
Bangalore, Karnataka
Hours/week
45 hrs/week
Application Deadline: May 23, 2026 1:51 PM
Job Description

Principal Accountabilities: (the 6-8 main areas of responsibility)

· Develop verification plan based on chip specifications.

· Setting up of Digital Verification flow for Full Chip, from scratch and ensure Spec Compliance.

· Design and develop verification systems, decomposition and hardware/software partitioning with focus on reuse and scalability

· Design of optimized digital blocks/verification components meeting functional, cost and low power constraints and ensure spec compliance.

· Develop TCL scripts and design constraints to perform synthesis, DFT insertion and static timing analysis.

· Support DFT strategy and implementation.

· Verification planning, feature extraction and verification test case development.

· Interface with P & R for digital hand-off and post layout verification.

· Develop test vectors for production test.

· Perform physical silicon device evaluation where necessary.

· Produce high quality documentation for own blocks.

· Develop work-around solutions where necessary to overcome device errata including documentation.

· Mentor and train digital verification engineers

· All other tasks as deemed reasonable by your manager some of which will be set during annual performance review.

Qualifications

10+ Years of experience in Digital Verification and UVM.

· Experience in Logic design /micro-architecture / RTL coding.

· Must have hands on experience with Power product design, synthesis and timing analysis for complex Analog Circuits.

· Experience in Verilog/System-Verilog is a must.

· Knowledge of verification methodologies, platforms and techniques, i.e. Functional Verification, ABV, Formal Verification, regression frameworks, UVM, FPGA is required.

· Experience working in semiconductor ideally PMIC or Audio with focus on mixed signal integrated circuits

· Hands on experience developing block and top-level timing constraints for STA and P & R sign off

· Knowledge of scan insertion and ATPG generation

· Understanding of design constraints and synthesis scripts

· Work independently on straightforward tasks, with little direction from manager

· Ability to propose innovative solutions

· Results-oriented and able to deliver on-time under a tight schedule

· Cross cultural awareness and sensitivity

· Proactive attitude about own role and contribution to company goals

· Ability to work both independently and part of a team

· Flexible to undertake occasional international travel at short notice

· Excellent command of verbal and written